Design Rules for Wafer Level Packaging of MEMS, CMOS-MEMS Integration, and Smart Systems using Anodic Bonding and Lateral Feedthroughs

The advantages of wafer level packaging (WLP) are widely recognized across a range of applications MEMS, IC’s Smart systems, CMOS-MEMS integration, System on Chip (SoC), Package in Package (PiP), Package on Package (PoP ) etc. Key benefits include true chip-size package, reduced cost of interconnects (by creating at wafer-level rather than back-end chip-scale packaging), and minimising test and burn-in costs (more efficient at wafer level). Many emerging applications particularly CMOS-MEMS integration demand high levels of hermeticity, achievable only with eutectic, anodic or thermocompression bonds. Significant differences between emerging applications and traditional MEMS WLP include CMOS compatibility, heterogeneous materials, and an increased number of I/O’s. The most common approach to WLP in these emerging applications involves through silicon vias (TSV’s) e.g. MEMS on CMOS stacks. TSV packages offer significant improvements in number of process steps, I/O density and package size, but via creation, filling, and inspection technologies are not mature and the costs of development and tooling are significant. For these reasons WLP with TSV’s is currently limited to high volume production (CMOS image sensors and flash memory stacks). This paper presents the design rules for chip to wafer (C2W) and wafer to wafer (W2W) WLP for high levels of hermeticity and small package sizes, suitable for low to medium production volumes and heterogeneous materials. All process steps are mature with low development and tooling costs. The scheme in figure 1 features a glass carrier wafer metallised with thin film gold tracks and bond pads onto which ASICS are flip chip bonded. An etched silicon cap wafer is then anodic bonded to the glass carrier sealing chips inside. By limiting thickness of transverse vias passing through the bond frame a high degree of hermeticity is achieved. The W2W approach is shown in Figure 2 C2W bonding offers significant increase in yield through the use of known good die, and is flexible in terms of die and wafer size and material whilst supporting chips from Multi-Project Wafers (MPW’s). Compact hermetic packages at wafer level using mature and robust processes is highly attractive for a range of applications, provided the limitations are addressed. The most significant limitation is the number of interconnects, as bond pads are only located at chip perimeter. The need for thin transverse vias through the bond frame means broadening the via if low impedence is required, further limiting the number of interconnects. The potential to damage CMOS devices during anodic bonding (electrostatic charge and temperature), has also been addressed and strategies identified to limit damage. The location of bond pads on the top face means wire bonding not flip chip. Tests were carried out to identify minimum via pitch, maximum metallization thickness and via/spacing ratio, leading to the specification of packaging design rules.